Sapienza PhD in ICT

Since 1982 – Engineering the Information Society -

Laboratory of Digital Systems (LSD)


Internet-of-Things (IoT) applications impose a strong, unprecedented demand for high-performance and/or power-efficient digital processing VLSI devices. Research activities carried out at the Laboratory of Digital Systems span all the abstraction levels of the digital VLSI design flow, namely hardware/software platform level, register transfer level (RTL) and circuit level.

Specific fields of competence covered at LSD lab are:

  • Advanced embedded HW/SW development:
    • Linux, Embedded Linux, kernel programming, driver development
    • ARM, PIC, STM32 embedded system SW development
    • Zigbee-compatible wireless-sensor-networks
  • Architecture modeling/evaluation (single- & multi-core):
    • ARM, Leon, ST200, domain-specific (e.g. fuzzy, DSP)
    • Modeling languages: QEMU, SystemC, C, VHDL
  • RTL semi-custom IP design and IP integration:
    • arithmetic units, codecs, JPEG2000 compression, neural architectures
    • FPGA and ASIC flow (primarily VHDL based)
  • Circuit design:
    • CMOS cell design, timing, power, reliability analysis (SPICE level)
    • Self-timing, delay insensitive logic, globally-synch-locally-synch.

Research topics include:

  • Performance optimization of microprocessor platforms in specific applications;
  • Power optimization, low voltage microarchitectures;
  • Variability aware circuits and microarchitectures;

Facilities avalaible at LSD lab are the following:

  • HW Facilities:
    • 200MHz Digital Oscilloscope
    • 100MHZ Logic state analyzer
    • PCB development tools
    • FPGA Xilinx Spartan6 dev. boards
    • FPGA Xilinx Virtex dev. boards
    • STM Nucleo (ARM Cortex M3) dev. boards
    • Microchip PIC32 and DSPic dev. boards
    • Intel Galileo dev. boards
    • Raspberry Pi dev. boards
    • Atmel AVR (ATmega) dev. board (in house design)
    • FPGA Spartan3 dev. board (in house design)
  • SW facilities:
    • Cadence/Synopsys design flow (PDK ST 45nm, ST 28 nm)
    • Xilinx ISE design flow
    • Modelsim/Questasim/Synplify VHDL envinronment
    • HSPICE, NGSPICE, SPECTRE circuit simulators
    • QEMU, MPARM, SoCLib architecture simulators
    • gcc embedded cross toolchains
    • Microchip MPLAB

Available PhD research topics can be summarized as the design and modeling of power-aware and variation-aware microprocessor architectures and circuits for IoT.
Visit the LSD lab at http://vlsi.diet.uniroma1.it.

For further information on how to join, please contact the researchers at LSD lab: